Memory selection apparatus

ABSTRACT

Electronic selection circuits for operating coincident-current magnetic memories, and like apparatus, are provided for construction essentially entirely as integrated circuits, even the output drive stages. The circuits are arranged to transform ground referenced input signals to output signals for driving floating reactances without the transformers required in the prior art for voltage isolation. Further, the new circuits drive these reactive loads without excessive power dissipation or excessive transient voltages.

United States Patent [1 1 Jordan, Jr.

[451 Aug. 7, 1973 1 MEMORY SELECTION APPARATUS [75] inventor: William F.Jordan, Jr., Wellesley,

Mass.

[73] Assignee: Honeywell, Inc., Minneapolis, Minn.

[22] Filed: Dec. 7, 1970 [21] Appl. No.: 95,904

Related US. Application Data [60] Division of Ser. No. 675,081, Oct. 4,1968, Pat. No. 3,588,851, Continuation-in-part of Ser. No. 536,736,March 23, 1966, abandoned, Continuation-impart of Ser. No. 536,921,March 23, 1966, abandoned.

[52] US. Cl. 3117/215, 307/213, 307/218, 307/270, 307/300 [51] Int. Cl..H03k 19/36, H03k 19/24, H03k 17/04 [58] Field of Search. 307/213, 215,218, 307/270, 280, 300, 299 A [56] References Cited UNITED STATESPATENTS 3,209,214 9/1965 Murphy et a1. 307/213 X 3,217,181 11/1965 Zuk307/299 A 3,300,658 1/1967 Slusher et a1. 307/297 3,510,685 5/1970Watanabe et al..... 307/215. X 3,439,186 4/1969 Seelbach 307/215 X3,427,474 Chua.. 307/218 X 3,229,119 1/1966 Bohn et a1. 307/215 X3,233,125 2/1966 Buie 307/215 3,275,854 9/1966 Ciancio1a.. 307/300 X3,394,268 7/1968 Murphy 307/213 X 3,417,260 12/1968 Foster, Jr.. 307/215X 3,417,262 12/1968 Yao 307/213 X 3,482,111 l2/1969 Gunderson et a1.307/213 X OTHER PU BLICATIONS Sylvania Universal High-Level Logic,Sylvania Publication (SUHL), p. 1-4, Feb. 5, 1965.

Primary Examiner-John W. Huckert Assistant Examiner-L. N. AnagnosZtiornejr -W. Hugo Liepnianri and Fied Jacob [57] ABSTRACT Electronicselection circuits for operating coincidentcurrent magnetic memories,and like apparatus, are provided for construction essentially entirelyas integrated circuits, even the output drive stages. The circuits arearranged to transform ground referenced input signals to output signalsfor driving floating reactances without the transformers required in theprior art for voltage isolation. Further, the new circuits drive thesereactive loads without excessive power dissipa tion or excessivetransient voltages.

4 Claims, 9 Drawing Figures PMENIEB M19 7 I975 SHEET 6 OF 8 6?.7 @Qhjamass 2.0m nip [:1 El U E! G mamas DEBUG SUEDE EZIE] @UUEJU G E] 5|2LINES [:JUEJDEI EUUUEJ it] I E U [:1 [:1 [:l i 64 UNES G U GLINES wMEMORY SELECTION APPARATUS This application is a division of Ser. No.675,081, filed on Oct. 4, 1968, now U.S. Pat. No. 3,588,851, whichapplication was a Continuation in Part of Ser. Nos. 536,736, and536,921, both filed on Mar. 23, 1966 and owned by the Assignee hereof,and now abandoned.

This invention relates to selection circuits for operatingcoincidentcurrent magnetic memories and like electrical devices. Inparticular, it provides such circuits that can be fabricated essentiallyentirely with monolithic integrated construction even on a commercialscale, i.e., in relatively large quantity and at industry-wisecompetitive cost. The monolithic construction enables the circuits to becompact; and because signal paths therein are short, they are fast.

The selection circuits of the invention also provide advantages inperformance and cost, whether constructed as integrated circuits orotherwise, e.g., with discrete components.

When used to operate a coincident current magnetic memory, the selectioncircuit performs the decoding, drive and switching operations with whicha pulse of current of selected polarity is applied to one line of thememory in response to address and read-write control signals.

Integrated circuits are known to provide economies in cost and size forelectronic circuits. However, they have limited tolerence to heatdissipation and to reverse voltage on semiconductor junctions. Also,inductors, and particularly coupled inductors as used in formingtransformers, are not readily fabricated with integrated construction.

These problems have restricted the use of integrated circuits,particularly for operating coincident current memories. This is becausesuch memories present reactive impedances to their driving circuits,which consequently must develop relatively large currents to switch suchloads. Also, prior circuits have developed relatively large transientvoltages when switching such loads, and it is costly and relativelydifficult to fabricate semiconductor junctions by means of integratedcircuit techniques which withstand such voltages. Another problem isthat the voltage isolation desired in such circuits between the groundreferenced input signals and the output signals, the potentials of whichare load and time dependent, has heretofore been considered to be besthandled by resort to isolation transformers. But transformers are notreadily fabricated by means of integrated circuit techniques.

Also in the prior art, a conventional circuit for selecting onecorethreading line in a core memory employs two voltage supplies ofsymmetrical voltages, i.e., +v and v. Two pairs of switches per line areoperated to apply current from one of the two supplies to the line,according to the desired current direction. With this prior arrangement,faulty logic or a malfunction can place both supplies in series, whichcan result in destructive circuit damage, particularly to thetransistors forming the switches. v

Further, it is an unfortunate drawback that the leads from acoincident-current memory are necessarily abundant. These leads run toselection and driver components for providing read-write currents to theselected storage element. Due partly to the amount of lead lengthrequired, with inherent stray capacity and inductance, and partly toinductance and drive requirements of the storage elements, the necessarydrive power has heretofore required utilization of a large number ofdiscrete circuit elements.

As used herein, discrete elements are defined as circuit elements suchas transistors, diodes, resistors, and capacitors that existindividually, in individual physical packages. This is in opposition tointegrated circuit elements, which are formed simultaneously with othercircuit elements and their interconnections in a single physicalpackage. A monolithic integrated circuit is an operative configurationof interconnected components formed on a single block of semiconductormaterial. Commonly the block is a chip of silicon measuring about 1 tol0 square millimeters in area with the circuit formed by diffusion andevaporation techniques.

The use of discrete circuit elements produces a volume and packagingproblem that makes it difficult to unite the drive and selectioncircuitry of a memory in really close proximity to, or in the samephysical package or module with, the memory elements with which thecircuit operates.

Now in accordance with the present invention, selection circuitry formagnetic storage media are provided which are adapted for economicconstruction essentially entirely as monolithic integrated circuits.This is obtained by a minimal power-dissipation form of circuit that canbe incorporated in the same monolithic chip, if so desired, with thedrivers for a plurality of drive lines of a magnetic core or likememory. in one embodiment, four drive transistors with their associatedcircuitry are incorporated in a single monolithic element.

The result of essentially complete utilization of integrated circuitelements for decoding, driving and lineisolating functions in accordancewith the invention is a complete functional computer memory ofsurprisingly small size. If desired, the circuitry and the magneticstorage media can be packaged on a single printed circuit wiring board.One result is that many prior art interconnecting leads are eliminated,and others can be replaced with printed circuits; both providing greaterstability and reliability. The reduced lead length results in decreasedstray inductance and capacitance. Also, both operating speed and powerrequirements are improved.

It is an object of this invention to provide a memory selection circuitof comparatively low cost and comparatively small size. The circuitshould be suited for largescale commercial production. In particular, itis an object to provide such a circuit for operating acoincident-current magnetic memory.

Another object of the invention is to provide a coincident'currentmemory selection circuit suited for construction substantially entirelyas an integrated circuit. Specifically, it is an object to provide thedecoding, drive and switch portions of such a circuit suitable formonolithic integrated construction.

A further object of the invention is to provide circuits for operatingcoincident-current memories and like devices which have improvedperformance relative to prior circuits of this type. In particular, itis an object to provide such circuits that develop comparatively lowtransient voltages even when driving reactive loads. Another specificobjective is that the circuits have relatively low vulnerability todestructive damage in the event of component breakdown or erroneousoperation.

A further object is to provide a selection circuit of the foregoingcharacter operating with relatively high electrical efficiency,particularly having relatively low average power dissipation.

It is another object of the invention to provide a circuit of the abovecharacter capable of relatively fast switching of reactive loads, and inparticular of corethreading memory lines.

It is also an object of the invention to provide a circuit of the abovecharacter providing efficient operation in response to ground-basedinput signals without the use of discrete inductive elements ortransformers.

Further objects of the invention are to provide a sink drive circuit fordriving one end of a line in a magnetic storage array and which can beimplemented essentially entirely with integrated circuitry; and toprovide a switch drive circuit for driving a second end of a line in amagnetic storage array that also can be implemented essentially entirelywith integrated circuitry.

Other objects of the invention will in part be obvious and will in partappear hereinafter.

The invention accordingly comprises the features of construction,combinations of elements and arrangement of parts exemplified in theconstructions hereinafter set forth and the scope of the invention isindicated in the claims.

SUMMARY OF THE INVENTION In accordance with the invention, a selectioncircuit for operating a coincident-current magnetic memory and likeelectrical devices is provided that can be, fabricated with integratedcircuit techniques. The circuit has the low power dissipation and thefreedom from excessive transient voltages desired for high reliabilitywith integrated components. However, the circuit has active feedbackpaths automatically operative during turn-on transients to expedite thisswitching operation. Other elements of the circuit automatically operateduring turn-off transients to hasten the return to the off condition.

In addition, the selection circuit applies current of a selectedpolarity to a core-threading memory line from a single supply, ratherthan from a symmetrical pair of supplies as in the prior art. With thisnew arrangement, erroneous switching operation does not produce thedestructive damage likely with prior circuits.

These and other features described herein below enable memory selectioncircuits to be fabricated essentially entirely with monolithicintegrated construction. Such circuits embodying the invention arehighly compact and are well suited for relatively high volumemanufacture at comparatively low cost. Further, they are capable of fastoperation and they facilitate compact and electrically-efficient and lowcost connection to the memory they operate.

BRIEF DESCRIPTION OF FIGURES For a fuller understanding of the natureand object of the invention, reference should be had to the followingdetailed description taken in connection with the accompanying drawings,in which:

FIG. 1 is a functional block diagram of a digital computer;

FIG. 2 is a schematic representation of a portion of a selection circuitembodying the invention;

FIG. 3 is a simplified schematic representation of the sink circuitportion of FIG. 5;

FIG. 4 is a simplified schematic representation of the switch circuitportion of FIG. 5;

FIG. 5 is a schematic diagram of a selection circuit embodying theinvention;

FIG. 6 is a functional symbolic representation of the FIG. 5 circuit,

FIG. 7 is a block diagram of a multi-bit core memory embodying featuresof the invention;

FIG. 8 is a simplified showing of a magnetic core stack embodyingfeatures of the invention; and

FIG. 9 is a schematic diagram of another selection circuit, similar tothat of FIG. 5, embodying features of the invention.

DESCRIPTION OF PREFERRED EMBODIMENTS FIG. 1 is a block diagramrepresenting a conventional digital computer. A program block 10represents the input facilities that perform the programming functions.A timing and control unit 11, an address register 12, and a dataregister 13 all receive program instructions i.e., control signals. Afast access memory indicated generally at 15 includes the blocks withinthe dashed outline. Memory 15 is depicted as one of a large number ofcommon and essentially identical units operated in conjunction with thesame timing, address and data units.

Memory 15 generally comprises one or more memory matrices l6 andselection and drive units 18 and 20. Each memory matrix usually containsmany thousands of binary switch elements such as magnetic cores. Thecores are threaded in a matrix on conductive leads termed lines. Aspecific core is selected by applying drive current on two lines boththreading, i.e., having windings on, the specified core. Current isapplied in one direction for a write operation and in the reversedirection for a read" operation. Line isolating networks 17 and 19,constructed for example, as conventional two-diode-per-line" networks,provide a reduction in equipment by restricting current to a singledesired path for both read and write operations. Current is applied tothe lines by drive switches which in turn are enabled by decodingcircuitry. Current is applied along one line by an X decoding,selection, and drive unit 18 and along the intersecting line by a Ydecoding, selection, and drive unit" 20.

The only feature in FIG. 1 that distinguishes it from conventionalcomputers is the position of the dashed line defining memory 15. Inaccordance with one aspect of the present invention, all the functionsindicated in memory 15 can be performed with circuits constructedsubstantially entirely as integrated circuits and hence capable ofassembly in a remarkably small package even, where desired, on the samecircuit card which carries an array of cores. (This construction assumesthat the memory matrix 16 is built up of plural planes of threadedmagnetic cores, the cores in each plane being threaded with X and Ylines in a rectangular configuration of rows and columns, respectively.)

The block diagram, FIG. 1, depicts what is called a 2%D memoryorganization. By way of comparison, one common early memory organizationusing magnetic cores is the 3D system in which each core carries fourwindings: X-axis winding, Y-axis winding, inhibit winding and sensewinding. In a PhD memory, the windings are reduced to three byeliminating the inhibit winding and adding the inhibit function to theY-axis input logic. In FIG. 1 this is indicated by the input to the Yunit 20 from data register 13. However, the decoding, selection, anddrive circuits of the present invention can be utilized equally well in3D and other memory organizations.

The interconnections between the registers 112 and 13 and the unit iiiand the memory K5 are not described in detail, nor are the programming,register and timing units described, since various conventionalconfigurations of these components can be utilized within the scope ofthe invention.

FIG. 2 is a partial schematic representation of the inventive memory 15depicting a few of the matrix lines 245 for one axis with magneticstorage elements 22 represented by short transverse marks on one matrixline 21. It will be understood that in practice a memory may have manymore lines and each line threads a number of storage elements. Typicallythe storage elements run to over one thousand per line.

One end of each line 24! is connected through an isolating diode to aswitch and through another isolating diode to a sink transistor. Forexample, one endof line 21 is connected through an isolating diode 23 toa switch transistor 25 and through an isolating diode 26 to a sinktransistor 27. It is to be understood that all of the switch transistors25 and sink transistors 27 are transistor switches. The terms switch andsink are arbitrarily chosen to distinguish the switched potentiallevels. The sink transistor switches to a common ground referencepotential. The switch transistor switches to a potential, illustrated aspositive, different from the common ground level. Isolating diodes 23and 26 can be made in the form of a monolithic chip flat pack 28. Thatis, these diodes can be fabricated on a single chip of semiconductormaterial and the chip packaged as a conventional flat pack. In theembodiment illustrated, this flat pack 28 contains sixteen diodesconnected to eight matrix lines. Switch 25 and sink 27 are also suitablymade in the form of a monolithic chip 30 comprising two switches and twosinks. Monolithic chip 30 also includes decoding circuitry which will bedescribed in detail with relation to FIGS.

3, 4 and 5. V

With further reference to FIG. 2, lines 24 are also each connected at anopposite end to a.further switch transistor and sink transistor. Forexample the upper most line 211 is connected to a sink transistor 31 andthrough a diode 32 to switch transistor 33. Sink transistor 3i andswitch transistor 33 are formedin a monolithic chip 35 identical to chip30. Diode 32 is a reverse voltage protection device to protect thebase-emitter junction of switch transistor 33 against reverse voltagebreakdown. Integrated circuit diodes 23 perform this function withrespect to switch transistor 25. Diode 32 is preferably a discreteelement since integrating it into chip 35 would significantly increasethe thermal dissipation requirements of the chip.

The remainder of the circuitry in FIG. 2 is merely a repetition of whathas been described with the exception of the electrical supplyarrangement, at the top of the drawing, now to be described.

In order to draw a known current essentially independent of the memoryimpedance, it is generally desirable to operate a magnetic storagematrix from a constant current source or at least a source with somecurrent regulation. This is commonly achieved by using a higher thannecessary voltage with a current limiting resistor. When used withmonolithic integrated circuits, thistechnique allows undesirably highvoltages to appear between detail portions of the monolithic chip e.g.,between two electrodes of a transistor. That is, the conventional supplyarrangement of a higher than necessary voltage supply and a currentlimiting resistor results in the development of undesirably highvoltages across the semiconductor material constituting the diodes 23and 2d and the source and sink transistors.

in accordance with one feature of the invention depicted at the top ofF116. 2, a current source is provided by a discrete element currentlimiting resistor 36 connected at one end 3d to a source 37 of arelatively high voltage and clamped at the other end dll by a discreteelement diode d ll to a lower voltage at terminal 39. End d1 of resistoran is the current source terminal for the matrix lines. Clamp dtliprevents the voltage across the semiconductor elements 2%, 3th and 35from exceeding the lower voltage at the resistor end M. It should beunderstood that the designation of elements such as the resistor 36 anddiode 4th as discrete is not necessary to practice the invention; itmerely denotes a preferred embodiment of the invention.

As also shown in FIG. 2, a further-diode 43 is in series between thesupply terminal til and the switch transistor 25. It is provided so thatcurrent applied to any line 2d from this supply terminal M passesthrough the same number of diodes regardless of the direction of thecurrent in the line 2d.

In operation, line 211 is selected with current directed from left toright (FIG. 2) by turning transistors 25 and 31 on. The resulting lowresistance path from ground 42, through the emitter-collector circuitsof transistors 31 and 25, to terminal ill reverse biases clam'p diode40. The circuit then operates as though the clamp diode did not exist.When transistors 25 and Eli are turned off, the voltage at terminal dllagain rises to the clamp voltage, at which point diode 40 again conductsforward current, preventing further voltage increase.

It was previously supposed that with no current in line 21 at theinstant the transistors were turned on, a voltage of about 24 volts wasnecessary to ensure a fast rise time, i.e., a rapid turning on of thetransistors. Close observation and analysis of prior circuits inoperation revealed that the voltage at terminal ill in the absence ofclamp dd dropped immediately to about 14 volts as soon as any one of theswitch transistors was turned on. The reason for the voltage drop waseventually determined as capacitive loading by the unswitched lines 24.

For example, as soon as transistor 25 is turned on, stray capacitancebetween all the lines connected to di odes 23, and from these lines toground, discharges through those diodes and the conducting transistor25. This produces significant clamping during the current rise time sothat the voltage at terminal dll does not attain the level at whichdiode W is conductive. Under these conditions, the addition of clampingdiode 4% has little effect on rise time. However, the higher voltagefrom source 3'7 clamped with diode W through the current limitingresistor 36 is still desirable to provide a stable current through theselected lines after the transient rise interval.

The clamping diode 4ND is of particular importance when all of theswitches connected to the particular source are turned off,disconnecting all lines. In the absence of clamping diode 40 under thiscondition, the voltage at terminal 41 would rise to the full sourcevoltage applying, in the illustrated example, 24 volts across thesemiconductor elements to which it is connected. Clamping diode 40,however, prevents this voltage from ever exceeding a predeterminedrelatively low level, for example, 14 volts.

Thus, reviewing the circuit of FIG. 2, in each group of four memorylines 24 connected with a switch-sink transistor pair on a monolithicchip 30, one memory line 21 is selected with current directed from leftto right by turning on transistors 25 and 31 and having transistors 27and 33 turned off. This applies the voltage at resistor end 41 to thecollector of transistor 25 with the result that current successivelypasses from the source 37 through resistor 36, diode 43, transistor 25collector-emitter path, one diode 23, to the line 21 and throughtransistor 31, from its collector to emitter, to the common ground 42 towhich the source 37 is returned.

Similarly, turning on only transistors 33 and 27 applies thesame-magnitude current through line 21, but directed from right to leftin FIG. 2. From the source 37, the current successively passes throughthe transistor 33, diode 32, line 21, one diode 26, and transistor 27.

In either of these operating conditions, the current in line 21traverses resistor 36. However, the low impedance of the conducting pairof transistors 25 and 31 or 27 and 33, and of the elements between them,holds the voltage at the resistor end 41 to below the value at which thediode 40 conducts appreciable current.

When all transistors 25, 27, 31 and 33 are off, so that essentially nocurrent is applied to any line 24 in circuit with them, the diode 40 isbiased to conduction and clamps the voltage at the resistor end 41 tothe desired maximum level. The resistor 36 conducts the diode clampingcurrent.

With this arrangement, the voltage across the transistors 25, 27, 31 and33, and across the diodes 23 and 26, never materially exceeds the valueto which the diode 47 clamps the resistor end 41. Further, the dynamicrange of voltages across these transistors and diodes is essentiallyonly between this clamped voltage and the common ground 42.

If two transistors 25 and 27 or 31 and 33 should conduct simultaneouslydue to some fault, the current through them is limited to the samenominal value normally conducted. Hence, this fault condition is notmaterially different from the desired operating conditions describedabove inasmuch as two transistors are in series between the resistor 41and the common ground 42 in both instances. As a result, this faultcondition is not likely to damage any circuit components.

A further feature of the FIG. 2 circuit is that a single supply i.e., asingle combination of the source 37, resistor 36 and clamping diode 40,is sufficient to operate many memory lines 24; there are 16 in theillustrated relatively simple embodiment. This results in a saving ofcircuit components with a corresponding saving in cost, weight, spaceand dissipation.

FIG. is an essentially complete schematic representation of anembodiment of the selection circuit for block 30 in FIG. 2 and capableof monolithic integrated 'circuit construction; block 35 of FIG. 2preferably employs identical circuitry. However, before considering FIG.5, FIGS. 3, 4 and 6 pertaining to it will be described, starting withFIG. 6 which is a symbolic representation of the elementary logicfunctions performed with the FIG. 5 circuit.

In FIG. 6, three address signals are applied to terminals 90, 91, and 92for selecting the block 30 out of a group of (2) or eight such blocks.The terminals 90, 91 and 92, when they receive assertion level signals,operate a coincidence gate 102 to apply an assertive output signal toone input terminal on each of four coincidence gates 48, 70, 148 and170. The single output signal from each of these gates operates, whenassertive, a transistor 27, 25, 127' and 125 respectively. These are thesame transistors 27, 25, 127, 125 shown in FIG. 2.

A further address signal applied to terminal 95 in FIG. 6 enables thegates 170 and 148, and a like address signal applied to terminal 101enables the two gates 70 and 48. The Read control pulse is applied to aterminal 94 to operate whichever of gate 70 and 170 is simultaneouslyreceiving assertive signals on its other two input terminals. Likewise,a Write control pulse is applied to a terminal 93 to operate whichevergates 48 and 148 is simultaneously receiving assertive signals on itsother two input terminals.

The FIG. 6 terminals 96, 97, 98 and 100 connect to the FIG. 2 diodeblock 28 as indicated in FIG. 2. The connection of the block 30 to thesupply shown at the top of FIG. 2 is also indicated in FIG. 6.

Thus, by way of example, the coincidence of three assertive addresssignals at terminal 90, 91, and 92, and at terminal 95, plus a Writepulse at terminal 93, activate the coincidence circuit'148. Itsresultant output signal turns on transistor 127 to provide alowimpedance path to ground from the terminal 96.

FIGS. '3 and 4 show portions of the FIG. 5 selection circuit. In thedetail circuits of FIGS. 3, 4 and 5, the reference numerals 48, 70, 148,and 102 used in FIG. 6 to denote coincidence gates are used withreference to multiple-emitter transistors that provide the logicalcoincidence function.

FIG. 3 shows the circuitry associated with the sink transistor 27 ofFIG. 2 and represented in FIG. 6 with the gate 48 and transistor 27. TheFIG. 3 impedance 63 represents the core memory, i.e., the core-threadinglines 24 of FIG. 2, and the diodes 23 and 26 in the FIG. 2 block 28. Thecircuit applies current to this impedance when both the FIG. 3 sinktransistor 27 is conducting and switch 47, which represents any onetransistor switch such as the transistor switches 33 and 25 of FIG. 2,is closed (i.e., the switch transistor is conducting).

The circuit is basically an amplifier actuated when all inputs on leads49 are positive. When actuated, for the purpose of reducing tum-on time,the circuit overdrives the transistor 27 until it becomes saturated.When the transistor 27 is turned off, the circuit discharges transientcurrent from the inductive impedance 63 without subjecting anycomponents to excessive, and hence potentially damaging, voltages orcurrents. Moreover the transient discharge path reduces system noisevoltages. These features enable the circuit to attain fast operationwith a relatively highly reactive load 63 with only relatively lowdissipation requirements and relatively small peak voltages andcurrents, even during switching transients.

More specifically, a multi-emitter transistor 48 in FIG. 3 is connectedat the input of the circuit to provide a selection function. It has twoor more emitters connected to inputs leads 49. The base 50 is connectedthrough a current limiting resistor 51 to a terminal 52 connected to thetap 39 on the source 37 described above with reference to FIG. 2. Thecollector of transistor 48 is connected directly to the base oftransistor 55.

The collector of transistor 55 is connected through a resistor 58 tosupply terminal 52 -and also through resistor 60 to the cathode of adiode 61. The anode of diode 61 is in turn connected to the emitter of afurther transistor 62. The emitter of transistor 55 is connected througha resistor 53 to common ground 42 and also by a direct connection to thebase of transistor 56.

Where the elements in the block 30 are fabricated on a singlesemiconductor chip, i.e., with monolithic integrated construction,common ground 42 is common to the reference substrate of the chip.

The emitter of transistor 56 is connected to the base of transistor 27and also through a resistor 57 to the common ground 42. Transistor 56 isconnected with its collector floating for use as a diode. The emitter oftransistor 27 is connected to common ground, while the collector isconnected to an output terminal 100. The collector of transistor 27 isalso connected through a resistor 66 to the cathode of a diode 67. Theanode of diode 67 is connected to the emitter of transistor 62.Transistor 62, which may be shared by two or more of these circuits asshown in FIG. 5, has a collector connected to supply terminal 52 and abase connected through a resistor 65 to supply terminal 41.

In FIG. 3, the dashed line 45 shows the division between the circuitryconnected to transistor 27 and illustrated as fabricated on block 30 inFIG. 2, and other memory circuitry connected with it. For example,switch 46 is representative of other sink transistor circuits, whileswitch 47 represents other switch transistor circuits. Resistor 36 anddiode 40 are the same as those illustrated in FIG. 2 along with supply37.

Considering the operation of the FIG. 3 circuit, the multiple emittertransistor 48 serves as an input AND gate. All emitters on transistor48, which may be two as illustrated, or more, must be gated off bysignals that are positive with respect to the potential of baseelectrode 50, in order for sink transistor 27 to conductor. With allemitters of transistor 48 gated off, current from the positive supplyterminal 52 passes through the bias resistor 51 and the forward-biasedcollector-base junction of transistor 48 to bias transistor 55 on,-i.e.,into conduction.

Transistor 55 provides gain and together with transistor 56 operates toprovide noise immunity inthe operation of transistor 27. This is becausetransistor 56, connected as a diode, provides an essentiallycurrentindependent voltage drop, thereby increasing the input signalnecessary to operate transistor 27. Hence the accumulatedbase-emitterdrops of transistors 55, 56 and 27 is sufficiently large substantiallyto preclude noise voltages at the base of transistor 55 from causingoperation of transistor 27.

Resistor 57 provides a discharge path for the input capacity, moreprecisely for the stored charge, of transistor 27, and a resistor 58connected from the collector of transistor 55 to supply terminal 52provides the operating current for transistor 55.

Thus, when all inputs to the emitter of transistor 48 are positiverelative to the base 50, the transistor 55 conducts and switches thetransistor 27 to conduction.

Its collector then drops from its normally positive potential to apotential near the ground level at the emitter.

When the memory matrix, represented as load 63, is not receivingcurrent, terminal 41 will be clamped at approximately the same voltageas supply terminal 52. This clamped voltage at terminal 41 issufficiently positive to bias transistor 62 to conduct current from thesupply terminal 52; through diode 61 and resistor 62, to the collectorof transistor 55. However, so long as transistor 55 is not conducting,this current through transistor 62 is nil. On the other hand, as soon astransistor 55 is switched to conduction and before transient conditionsterminate so that the voltage at terminal 41 drops toward the steadystate on" value, transistor 62 provides additional current for thecollector circuit of transistor 55, increasing to the current in itscollector and hence at its emitter; resistor 60 is suitably selected toprovide an equal current path as provided through resistor 58. The endresult is increased drive current for sink transistor 27 and is referredto hereinafter as overdrive.

When current is applied to the matrix by closure of the switch 47 andturning on of transistor 27 and the turn-on transients settle, thevoltage at terminal 41, connected to the base of transistor 62, drops.This in turn reduces conduction of transistor 62, thereby removing theoverdrive current applied to the collector of transistor 55. The purposeof this arrangement is to provide overdrive current during turn-on ofsink transistor 27. With resistor 60 and resistor 58 approximatelyequal, the initial drive current through transistor 27.is thereby nearlydoubled. The subsequent automatic reduction in base drive current upondelivery of current to the matrix reduces the average power dissipationof the circuit.

The purpose of providing this overdrive to transistor 27 is to turn thetransistor on quickly, thereby initiating the desired memory operationwith minimal delay. This action is opposed by the inductive reactance ofthe memory load 63. Further, once the inductive memory reactance ischarged, the excessive drive that turns transistor 27 on quickly isunnecessary and, in fact, would result in undesirably high dissipation.The present circuit solves all these problems by providing overdriveautomatically only during the turn-on transient. The circuitautomatically initiates the overdrive current when transistor 55 turnson and automatically terminates it when the turn-on transient ends sothat the voltage at the base of transistor 62 drops. In this manner, theFIG. 3 circuit provides the desired high drive to transistor 27 forrapid turn-on yet maintains the continuous operation of transistor 27 ata low level where dissipation is minimal.

With further reference to FIG. 3, the base-collector junction oftransistor 62 forms a diode that serves the additional function of aprotective clamp shunting the clamp diode 40. That is, in case offailure of a clamp diode 40, the several transistors 62 associated withthat diode take over its clamping function. Diodes 61 and 67 serve asreverse voltage protection for transistor 62. Also, the collector oftransistor 27 (connected to the matrix load 63) is connected throughresistor 66 and diode 67 to the emitter of transistor 62. As describedhereinafter, this provides a reference potential for unloading matrixcapacitance when no current is applied to the matrix.

Diode 68 in FIG. 3 is intrinsic to the integrated monolithicconstruction of resistor 66 and acts as a diode with its anodeconnection distributed along resistor 66. In the construction of anintegrated circuit, a resistor is formed by a region of semiconductormaterial of a given conductivity type, e.g. with a selected impurity.This region is separated from the rest of the circuit by a layer ofopposite conductivity type semiconductor material which will be biasedto a fixed potential during operation. Connection is made to theresistor by electrodes at two spaced points in the region, and theresistance is determined by the geometry and resistivity of the region.The semiconductive materials, their conductivity type characteristics,and the fixed potential are so selected that the junction formed betweenthem is reverse biased during normal operation. This electricallyisolates the element from the remainder of the integrated circuit.However, schematically, the diode 68 is essentially connected betweenthe output terminal 100 and the supply terminal 52.

The intrinsic diode 68 is advantageous in damping inductive kicks fromthe matrix during switching of the current therein. That is, a highvoltage swing in the forward direction will cause conduction of diode68. The large area junction formed by the resistor 66 permits high peakcurrent with low voltage drop, thereby providing good protection againstovervoltage breakdown in transistor 27.

The FIG. 3 transistor 62 provides the further function of restoring theload 63 to a positive voltage after current therein is interrupted byturning transistor 27 off. During application of current to the loadthrough transistor 27, the load is at the near-ground potential of thetransistor collector. When the transistor is switched off, thebase-emitter junction of transistor 62 is briefly forward-biased. Hence,this transistor conducts through resistor 66 and the shunt capacitanceof the load 63. As a result, this. stray capacitance becomes charged tonear the voltage at terminal 41.

FIG. 4 is a more-detailed schematic representation of the FIG. 6 gate 70and switch transistor 25, in which switch transistor 25 is the same astransistor 25 in FIG. 2. Transistor 25 is arranged as an emitterfollower driven from a logical AND" input stage. This input stage is acommon base multiemitter input amplifier transistor 70 with gating butno inversion. In addition to providing the logical AND selectionfunction, transistor 70 provides voltage gain. It drives the threeemitter-follower transistors 78, 80 and 25 that provide an impedancetransformation, with direct coupled semiconductor elements exclusively(i.e., no transformers or the like), from the ground-based input signalsat transistor 70 to the floating emitter of transistor 25. The memoryload 63 is connected from this emitter to ground through the sinktransistor 27 in FIG. 3 or other switches 46 as shown in FIG. 4.

In particular, the plural emitters of transistor 70 are connected toinput leads 71. The base of transistor 70 is connected through resistor72 to a biasing supply that consists of a transistor 73 and voltagedivider resistors 74 and 75. The divider resistors tend to track withtemperature and supply a stable control to bias transistor 73, whichoperates as a constant voltage supply to transistor 70.

Collector 76 of transistor 70 is connected to supply terminal 52 througha resistor 77 and is connected directly to the base of transistor 78.Transistors 78, 80

and 25 are connected as a three-stage emitter follower for current gainand high input impedance. The collectors of transistor 78 and 80 areconnected through a resistor 81 to supply terminal 52. The collector oftransistor 25 is connected to supply terminal 41 and the emitter isconnected to the matrix load 63. Switch 47 represents other switchtransistor circuits.

As also shown in FIG. 4, a diode 82 is connected with its cathode toterminal 41 and its anode to the collectors of transistor 78 and 80. Afurther transistor 83 is connected as a diode with its cathode (theemitter) connected to collector 76 and its anode (the base andcollector) connected to the base of transistor 25.

In the operation of the FIG. 4 circuit, gating transistor providesvoltage gain while transistors 78, and 25 all provide current gain.Resistor 81 is selected to maintain saturation of transistor 25 duringthe switch on time and thereby minimize dissipation in the transistor.Diode 82 provides quick turn-on with the inductive load by increasingthe drive current through transistor 80 during the turn-on transient. Inparticular, when the transistor 25 is turned on, transistor 80 is alsoon, with its collector near the potential of the transistor 25 emitter.Thus, when the switch 46 closes, the relatively high clamped voltage atterminal 41 forward biases diode 82 so that it delivers current to thetransistor 80 collector in parallel with the current the transistornormally receives through the resistor 81. The sum of these two currentsapplied to the transistor 80 collector are applied to the base oftransistor 25 and hence to the load 63 through the transistor 25emitter. This overdriving turn-on operation stops when the turn-ontransient of the load 63 stabilizes, allowing the voltage at theterminal 41 to decrease, with the result that the diode 82 is no longersignificantly forward biased.

The transistor 83 in FIG. 4 functions as a turn-off diode thatdischarges parasitic capacity between transistor 80 and transistor 25and stored charge in these transistors. This speeds up the turn-offtransition, i.e., the cessation of current in the load 63 in response tocorresponding signals applied to the input transistor 70. In addition,when the transistor 70 is not applying an assertive signal to transistor78, so that transistor 25 should be non-conductive, the transistor 83functions as a diode preventing the transistor 25 base from becomingcharged positive, and hence maintains the transistor 25 reliably off.

In reviewing FIGS. 3 and 4, average operating power dissipation isgreatly reduced by the use of the overdrive circuits" for increasingdrive only during turn-on transients. The overdrive" is automaticallycancelled as soon as full turn-on is achieved so that drive power isreduced to a holding level. In FIG. 3 the overdrive is provided bytransistor 62 under control from terminal 41. As full load current isattained through the matrix load 63, the voltage at terminal 41decreases, cutting off the overdrive. In FIG. 4, diode 82 provides theoverdrive current to transistor 80, again in response to the voltage atterminal 41.

Referring now to FIG. 5, it shows a selection circuit which can befabricated as a monolithic integrated circuit. That is, all thetransistors, diodes, resistors, terminals and interconnections shown inFIG. 5 can be fabricated on a single body of semiconductor material withconventional bipolar integrated circuit materials and techniques. Asindicated in FIG. 6, the circuit incorporates two sink circuits of FIG.3 and two switch circuits of FIG. 4. The discrete elements separated inFIGS. 3 and 4 dashed lines 45 are of course not shown in FIG. 5 as theyare not part of the monolithic chip (FIG. 2). It will further be notedthat while all the other circuit elements of FIG. 3 are duplicated inFIG. 5, transistor 62 and resistor 65 only occur once in FIG. 5, whenthey are shared by both sink circuits. Likewise, transistor 73 andresistors 74 and 75 of FIG. 4 appear only once in FIG. 5 and are sharedby the two switch circuits. For convenience, the duplicated circuitelements in FIG. 5 appear in one instance with the same numbers used inFIGS. 3 and 4, in the other instance using the same number plus onehundred so that, for example, the sink transistors appear as transistor27 and transistor 127. The input AND gates are illustrated in FIG. 5using transistors of three emitters each instead of two as shown inFIGS. 3 and 4. The number of emitters can be varied according to thedemands of the input logic.

An additional input transistor 102 is shown in FIG. 5 with its baseconnected through resistor 103 to the emitter of transistor 73. Itscollector is connected to one emitter of each of input gate transistors48, 70, 170 and 148. Transistor 102 is a multiemitter transistor havingthree emitters connected to input terminals 90, 91 and 92 for addressand data signals, an illustration of which was previously consideredwith reference to FIG. 6. Transistor 102 serves the dual function ofreducing the required number of input emitters and the number ofcrossunder connections.

In this last respect it is pointed out that FIG. 5 shows literally thelayout and connectionv crossunders for a specific embodiment of themonolithic integrated circuit. In the absence of the required resistiveconnection, each connection crossunder required the addition of anextraneous resistance (not shown). Since in monolithic integratedcircuit design each added resistance for crossunder purposes is anadditional component supplying no other beneficial result, it is worthconsiderable effort to minimize connection crossunders. Referring againto transistor 102, it will be seen that the crossunderconnecting theemitter of transistor 73 to the base of transistor 102 can beaccomplished with the current limiting resistor 103. The crossunderbeneath the lead connecting the collector of transistor 102 to the inputcircuitry required the use of an extraneous resistance (not shown).

Terminals 93 and 94 'for connection to read/write timing signals areconnected with terminal 93 to one emitter of each of transistors 148 and48 and terminal 94 to one emitter of each of transistors 170 and 70.Thus terminal 93 is connected to the sinks and terminal 94 is connectedto the switches. Terminals 95 and 101 are further address inputconnections. Terminal 95 is connected to an emitter of each oftransistors 148 and 170 and terminal 101 is connected to one emitter ofeach of transistors 48 and 70.

The other terminals of the FIG. 5 monolithic chip are terminal 41 forconnection to the voltage developed with current limiting resistor 36and supply source '37 as will be remembered with reference to theprevious figures and which is clamped by diode 40 so that it cannotexceed a fixed voltage, for example, 14 volts. Terminal 99 is connectedto terminal 52 internal to the monolithic circuit and is for connectionto said fixed voltage, i.e., 14 volts. Terminal 42 is for connection toa common ground. Terminals 96 and are connected to the collectorelectrodes of transistors 127 and 27 for sink connections to the memorymatrix, and terminals 97 and 98 are connected to the emitter electrodesof transistors and 25 for switch connections to the memory matrix. Itwill be seen that in some cases terminals 96, 97, 98 and 1100 will beconnected into the memory matrix through line isolating matrices such asintegrated monolithic diode matrix 28 of FIG. 2. In other instances, asdepicted by the partial showing of a monolithic selection and drive chip35 in FIG. 2, the connection to the memory matrix will utilize onlydiscrete element diodes, such as diode 32, connected to terminals 97 and98, while the connections to terminals 96 and 100 could be directconnections.

The monolithic selection circuit of FIG. 5 connected to acurrent-limited and voltage-clamped supply source, as depicted atterminal 41 in FIG. 2, has the advantage of near fail-proof operation.The use of this single supply for both read and write currents preventsdamage possible with prior schemes having separate read and writesuppliers. Further, it is short-circuit proof in that any output can beshorted to ground without damage. The use of a common ground for inputlogic and for sink emitters enables the use of a standard 14-pinintegrated circuit flat pack. (It will be noted that the terminalsdepicted in FIG. 5 total 14.) The circuit is also heavily protectedagainst over-voltage transients by both internal and external diodes aspreviously described.

A comparison of theoperational and other characteristics of the presentintegrated selection and drive circuit with the presently commerciallyproduced circuit having the nearest operational characteristics andfunctions but using discrete element driver transistors operated fromtransformers is given in the following Table I:

Monolithic Prior Art Selection and Drive Worst case X sebup time 20 nsec30 nscc (switch) Worst case turn-on delay 20 nsec (sink) Worst caseturn-off delay 90 nsec 50 nscu (sink) Intercycle recovery time I00 nscc20 nscc (switch (transformer) parasitic capacity) Address input loading6 ma 6 ma (per 8K bit, assuming load sharing) Power dissipation I300 mw500 mw Worst case saturation 1.1 v 0.6 v voltage Worst case noise 1.1 vI.() v immunity (local ambient 60 C) Maximum voltage 30 v 17 v Maximumcurrent 400 ma 400 ma Packaging volume (actual) 4.125 in. 0.0625 in.

(Two flat packs) The integrated selection circuit of FIG. 5 providesinternal stack capacity discharge paths as has been described. An idlestack is referenced to the fixed voltage of terminal 99, i.e., to 14volts.

One problem in memory matrices which limits speed and increases powerrequirements is capacitive storage effects. The present inventionminimizes this problem by minimizing interconnecting lead lengths, ashas been previously described, and by the use of appropriate recoverycircuits and operational sequence control for providing optimumpotential recovery.

In a system such as will be further described in connection with FIG. 7,the Y lines are partially recovered through resistors such as resistor66 of FIG. 3 associated with the sink transistors. This can be seen inFIG.

2 in which connected to the collector of each sink transistor 27 and 31is a resistor referenced to a positive voltage. Referring back to FIG. 2it will be seen that one of these resistors is connected at each end ofeach Y axis line, for example, line 21 is connected at one end throughone of diodes 26 to the resistor in the collector circuit of transistor27 and at the other end directly to the resistor in the collectorcircuit of transistor 31.

Referring again to FIG. 3 it will be seen that the referencing of theseresistors is under the control of the voltage at terminal 41. When thetransistors are switched to terminate the current applied to a Y line,e.g., line 21 in FIG. 2, and before current is applied to another Yline, the voltage at terminal 41 rises to the clamping voltage of diode40. This clamped voltage is sufficiently positive to bias transistor 62to conduction, thereby providing a recovery path to the positivepotential at terminal 52 for the Y line 21. As a result, when current ina Y line is switched off, resistor 66 and transistor 62 (FIG. 3) operateautomatically to raise the line from the near-ground potential appliedto it during the application of current to a positive potentialcorresponding to the potential at terminal 52.

Thereafter, as soon as current is applied to a Y line, a voltage drop atterminal 41 disconnects the recovery path through transistor 62 toreduce power dissipation. As described below, a different recoverysystem is required for the X lines in the arrangement of FIG. 7 due tothe additional diode matrices at both ends of each line.

FIG. 7 illustrates a typical memory matrix in accordance with thepresent invention. The matrix shown is described as an 8000 word memorywith four bits per word. The number of bits per word can be increased bystacking as illustrated in FIG. 8.

Each block labeled S/D, such as block 200, represents a singlemonolithic selection circuit as illustrated in FIG. 5. Each blocklabeled I" such as block 201 represents a monolithic flat packcontaining two eightdiode line isolating matrices as illustrated byblock 28 in FIG. 2.

The X axis lines in the matrix go horizontally across the FIGURE andreturn as represented by single line 202. By doubling back in thismanner it will be seen that each X axis line, as depicted by line 202,crosses each Y axis line twice. One of the Y axis lines is indicated byline 203 and since there are storage elements at all intersections,there are two elements represented as 205 and 206 at intersections oflines 202 and 203. Drive block 200 has four output connections connectedin parallel to each of isolating blocks 201, 207, 208 and 210. Theseoutput connections are shown in FIG. 5 as output terminals 96, 97, 98and 100. The interconnections are in the manner shown in FIG. 2 betweenblocks 30 and 28. Since eight isolating lines are available at theoutput of each isolating block there are a total of 32 X lines derivedfrom the single drive block 200. It should be noted that the input linesto each isolating block from drive block 200 are parallel but the outputlines, eight from-each isolating block, go directly into the matrixwithout connection to other isolating blocks. Each X line, aftertraversing all of the Y lines twice, returns to another drive block 211.A single l6-diode isolating block 212 buffers the connection of the 32return lines to drive block 211.

Isolating block 212 is not needed to prevent read/- write interactionbut rather is used to segment part of the matrix capacitance from each Xline to reduce transient power dissipation. As shown in block 28 in FIG.2, there are eight two-diode-per-line line isolators in each of theisolating blocks. Thus, as indicated at the top of FIG. 7 for one of theeight lines input to block 212, with 32 lines coming into isolatingblock 212, four lines are connected in common to each of thetwodiode-per-line line isolators. This arrangement effectivelydisconnects three-quarters of the matrix capacitance from each X lineduring operation of any one line. The seven additional sets of 32doubled lines shown in FIG. 7 are each identical to the one described.

No description of the Y axis lines is necessary since they are describedin detail in connection with FIG. 2, which illustrates the Y axis linesfor a one-bit matrix. It will be seen that the FIG. 2 configuration with16 lines is repeated four times in FIG. 7 giving a total of 64 Y axislines. The number of Y axis lines multiplied by each traversal of an Xaxis line across the matrix determines the number of intersections atwhich magnetic storage elements are located. Accordingly, the matrixillustrated in FIG. 7 has a total of 32,768 storage elements.

With further reference to FIG. 7, a sense line for each data bit has awinding on each storage element in the data bit and is connected tooutput terminals for supplying sense information to a data register. Atleast one sensing wire is required for each data bit. Thus with fourdata bits to each word, there will be four sense wires and eight sensewire output terminals. In an actual matrix as depicted by FIG. 7, twosense wires were used for each data bit giving a total of 16 senseoutput terminals.

These 32,768 cores are readily mounted on a single printed circuit cardmeasuring about 5 X l 1 inches and leaving enough additional space formounting flat packs containing monolithic chips depicted by the S/D andI blocks in FIG. 7. However, the number of bits can be increasedconsiderably without addition to the X drive circuitry by usingadditional magnetic matrix cards in stacked formation in which thedifferent cards may be referred to as planes.

An illustrative embodiment of such an arrangement is depicted in FIG. 8,where the X axis drive and isolating circuits are arranged on a singlestack card 220. This separate card for X axis drive can be utilized instacks having various numbers of planes. The integrated X circuitry onthe card 220 is represented by an arbitrary arrangement of spots 212 onthe surface of the card with the X axis drive arrangement depicted inFIG. 8. These spots 212 represent the S6 monolithic chips mounted asflat packs on the card. X axis line 222 is connected to the X axis driveand isolating circuits in the same manner as the line 202 in FIG. 7.Thus it is connected at a first end 223 to an X axis drive connection oncard 220 and then traverses through the Y axis lines on seven planes ofmatrix cards 225, 226, 227, 228, 229, 230 and 231. At card 231 line 222re verses after traversing the card, recrosses the Y axis lines acrossall seven planes and returns to connect at its other end 232 to X axisdrive circuitry on card 220.

The integrated Y axis circuitry is illustrated in FIG. 8 as mounted onthe margins of the matrix cards of the respective planes and isrepresented by spots 233 and 235.

Referring back to the current supply source arrangement depicted in FIG.2 using resistor 36 and diode 40,

it has been a previous practice to use separate current limitingresistors for each polarity at current, i.e., to use one or moreseparate resistors for write current and likewise for read current. Itwas found that this prior arrangement allowed unnecessarily high supplyvoltage inside the drive circuits. To prevent this, diode clamp 40 wasadded. This arrangement for each drive circuit resulted in considerablepower loss through the clamps. It was then found possible to eliminatenot only the greater part of this power loss, but also to reduce thenumber of required components by a significant factor. This is becausememory matrices are commonly made up of groupings of drive circuits andassociated matrix lines arranged such that within each group only oneline can be operated at a time. An example of this is seen in the Y axissystem of FIG. 7, where the Y axis contains four groups of 16 lineseach. Each group is depicted in greater detail in FIG. 2 where it isshown that the lines are interconnected in a way that makes mutualexclusion a requirement, i.e., that allows current to be applied to onlyone line 24 at a time.

Consequently, in accordance with one aspect of the invention, a singleresistor 36 and a single diode 40 are used for the current sourceoperating all the drive circuits in one such mutually exclusive group.Since sometimes it is desirable to switch one end of a line slightlybefore or after the other end, the same current supply source is usedonly for the drive circuitry at one end of the lines in the group. Inany case, each resistor-diode source combination operates with aplurality of lines, e.g., with 16 lines. In normal computer-type memoryoperation, one or another of the lines in a mutually exclusive group isdriven over a substantial percentage of operating time. In addition, aslong as one such line is driven from a given current source, the voltageat the respective terminal 41 will be below the clamp level andessentially no power will be lost in the clamp current. Thus, with aplurality of mutually exclusive load circuits connected to each clampedsource as in FIG. 2, the clamps can be operated efficiently with lowpower loss.

FIG. 9 shows a modified embodiment of the selection circuit of FIG. 5.Circuit elements in FIG. 9 having identical counterparts in FIG. 5 aredesignated with the same reference numerals used in FIG. 5, whereascircuit elements in FIG. 9 not found in FIG. 5 are designated withreference numerals in the 300 count. The component layout of FIG. 9,which'can be applied directly to the layout of the integrated circuitstructure, differs slightly from FIG. 5 with the result that integratedcircuit cross-overs are reduced.

The FIG. 9 circuit is sufficiently similar to FIG. 5 that a descriptionof only the differences is in order. A first difference concerns thetransistors 83 and 183 connected with the switch transistors 25 and 125,respectively. In FIG. 5, transistor 83 is connected with its collectorand base tied together to operate as a diode. However, in FIG. 9 thetransistor 83 collector is connected, separate from the base, to thebase of transistor 80. Similarly, the transistor 183 collector isconnected to the base of transistor 180.

The new connection of transistor 83 in FIG. 9 provides enhanced turnoffof transistor 25 by improved removal of stored charge from transistor 25and from transistor 80 driving it. During the steady state conditionwhere transistor 25 is conducting collector-emitter current, thetransistor 03 emitter-base junction is reverse biased because thetransistor 25 base is at a smaller positive voltage than the transistorcollector 76. Hence the transistor 83 has a relatively large impedanceto its emitter from both its collector and its base.

However, when the emitter of transistor 70 is switched from a positivevoltage to near ground in order to turn transistor 25 off, thetransistor 70 collector also drops to near ground potential. Thetransistor 83 emitter-base junction is then forward biased. Hence thetransistor conducts and removes, by way of its base, stored charge fromtransistor 25. The base-emitter diode of transistor 83 subsequentlymaintains an off potential at the base of transistor 25.

The turn-off operation also requires the removal of stored charge fromtransistor 80 driving transistor 25. The transistor 03 in FIG. 9, whenconductive, provides a low impedance discharge path for this purposefrom its collector, connected to the transistor 80 base, to its emitter.Thus the modified FIG. 9 circuit discharges the transistor 00 at itsbase, rather than at its emitter as with the FIG. 5 configuration.

The discharging operation of transistor 83 in FIG. 9 is self-regulating.That is, when the transistor 03 collector-emitter impedance issufficiently large so that some stored charge in transistor 80 isconducted to the transistor 00 emitter and discharged through transistor83 by way of the transistor 03 base,the resultant additionalbase-emitter discharge current turns the transistor 83 on further. Thisreduces the transistors collector-emitter impedance thereby hasteningthe transistor 80 discharge directly from its base through the collectorof transistor 03.

With further reference to FIG. 9, a second difference from the FIG. 5circuit is that the base resistor I03 connected with the inputmultiemitter transistor 102 (lower left side of FIG. 9) is returned to alarger positive voltage than in FIG. 5. This is done by the addition ofan impedance buffer transistor 302 having its emitter connected to theresistor I03, its base connected to a further tap 304 on the resistor74-resistor voltage divider, and having its collector connected to theterminal 52 to which the supply applies positive direct voltage (seeFIG. 4). This arrangement enhances the turnon speed of the circuit bycharging the stray capacitance that exists from the transistor I02collector to ground to a more positive voltage than with the FIG. 5arrangement. The transistor 302 serves essentially the same function forresistor 103 as the transistor 73 does for the resistor 72 connectedwith transistor 70, that is, it minimizes the effect on the voltage atthe tap 304 due to variations in the current drawn by resistor I03.

A final difference between the FIG. 9 circuit and that of FIG. 5 is theaddition of a transistor 306 and a diode 300 to develop the overdrivecurrent applied to the sink transistor 27 during the turn-on transient.In particular, the resistor 60 and diode 61 shown in FIGS. 3 and 5 areomitted from the FIG. 9 circuit. The new transistor 306 senses thetransistor 27 collector voltage at its base. When this voltage issufficiently positive, which occurs with initiation of tum-on operation,transistor 306 applies overdrive current, from the supply terminal 52,by way of the transistor 306 collectoremitter path and through the diode308 to the collectors of both transistors 56 and 55. The diode 308serves the same reverse-voltage protection function as the diode 61 ofFIG. 5. And the use of the transistor 56 as a transistor in FIG. 9rather than as a diode in FIG. provides additional gain. More important,however, the elimination of resistor 60 from FIG. 3 and FIG. 5 decreasespower dissipation.

With this new arrangement, the feedback circuit providing the turn-onoverdrive current is responsive to the transistor 27 collector voltage.In the arrangement of FIGS. 3 and 5 on the other hand, the voltage atthe source terminal 41 controls this overdrive current.

In sum, the invention described above provides memory selection circuitscapable of extensive fabrication with monolithic integrated circuitstructure. The invention thereby provides important savings in size andweight over prior circuits. The integrated circuit capability of theinventive circuit also enables it to be constructed at comparatively lowcost, particularly on a large scale.

It should be noted that the circuits of the invention are notnecessarily limited to operation with memories. Their logical decodingand driving functions can be applied to other electrical devices. Alsothe magnetic storage medium as used herein comprehends magnetic cores,magnetic film, plated wires, plated rods and other magnetic media suitedfor data storage. Generally the magnetic media should be operative assmall selectable elements having a magnetic characteristic exhibiting ahysteresis loop for switching purposes.

The circuits provided by the invention also have advantageousperformance, particularly in terms of power dissipation, operatingspeed, ability to drive reactive loads and to withstand the resultantdynamic changes in output voltage and current. These advantages arerealized substantially independent from the type of construction, e.g.,discrete components or integrated components, employed.

While the invention has been described in relation to specificembodiments, various modifications thereof will be apparent to thoseskilled in the art and it is intended to cover the invention broadlywithin the spirit and scope of the appended claims.

Having described the invention, what is claimed as new and secured byLetters Patent is:

l. A monolithic integrated circuit formed in a single block ofsemiconductor material, said circuit comprising:

1. conductive means formed in said single block of semiconductormaterial and including at least two input terminals, an output terminal,and a supply terminal,

2. an output transistor formed in said single block of semiconductormaterial and having its emittercollector path serially connected betwensaid output terminal and said supply terminal,

3. semiconductor impedance transforming means formed in said singleblock of semiconductor material and having an input lead and an outputlead, said output lead connected with the base of said outputtransistor,

4. semiconductor coincidence means formed in said single block ofsemiconductor material and having input leads coupled to said inputterminals and an output lead coupled to said input lead of saidtransforming means, said semiconductor coincidence means in response tosignals applied to said input terminals enabling said transforming meansand controlling the emitter-controller conduction of said outputtransistor,

5. semiconductor feedback means formed in said single block ofsemiconductor material and receiving a feedback signal corresponding tothe signal at at least one terminal selected from said output terminaland said supply terminal, said semiconductor feedback means responsiveto said feedback signal for applying a selective overdrive signal tosaid transforming means for accelerating the switching operation of saidoutput transistor, and

6. impedance means including a resistor and diode having its anodeconnection distributed along said resistor, said impedance means coupledto said semiconductor feedback means and said output transistor fordamping inductive kick during switching of said output transistor.

2. A circuit as defined in claim 1 wherein said semiconductor impedancemeans includes a first transistor having its base as an input lead and asecond transistor having its emitter as an output lead, said firsttransistor when conductive enabling said second transistor, said secondtransistor when conductive providing an enabling input to said base ofsaid output transistor.

3. A circuit as defined in claim 2 wherein said semiconductorcoincidence means includes a third transistor having multiple emittersand a collector, said multiple emitters coupled to said input terminal,said collector coupled to said base of said first transistor, said thirdtransistor in response to signals applied to said input terminalsenabling said first transistor to conduction.

4. A circuit as defined in claim 3 wherein said semiconductor feedbackmeans includes a fourth transistor having a base and an emitter, saidbase coupled to said supply terminal, said emitter coupled to saidimpedance means and to the collector of said first transistor, saidfourth transistor when conductive applying a selective overdrive signalto said collector of said first transistor for accelerating theswitching operation of said output transistor.

1. A monolithic integrated circuit formed in a single block ofsemiconductor material, said circuit comprising:
 1. conductive meansformed in said single block of semiconductor material and including atleast two input terminals, an output terminal, and a supply terminal, 2.an output transistor formed in said single block of semiconductormaterial and having its emitter-collector path serially connected betwensaid output terminal and said supply terminal,
 3. semiconductorimpedance transforming means formed in said single block ofsemiconductor material and having an input lead and an output lead, saidoutput lead connected with the base of said output transistor, 4.semiconductor coincidence means formed in said single block ofsemiconductor material and having input leads coupled to said inputterminals and an output lead coupled to said input lead of saidtransforming means, said semiconductor coincidence means in response tosignals applied to said input terminals enabling said transforming meansand controlling the emittercontroller conduction of said outputtransistor,
 5. semiconductor feedback means formed in said single blockof semiconductor material and receiving a feedback signal correspondingto the signal at at least one terminal selected from said outputterminal and said supply terminal, said semiconductor feedback meansresponsive to said feedback signal for applying a selective overdrivesignal to said transforming means for accelerating the switchingoperation of said output transistor, and
 6. impedance means including aresistor and diode having its anode connection distributed along saidresistor, said impedance means coupled to said semiconductor feedbackmeans and said output transistor for damping inductive kick duringswitching of said output transistor.
 2. A circuit as defined in claim 1wherein said semiconductor impedance means includes a first transistorhaving its base as an input lead and a second transistor having itsemitter as an output lead, said first transistor when conductiveenabling said second transistor, said second transistor when conductiveproviding an enabling input to said base of said output transistor. 2.an output transistor formed in said single block of semiconductormaterial and having its emitter-collector path serially connected betwensaid output terminal and said supply terminal,
 3. semiconductorimpedance transforming means formed in said single block ofsemiconductor material and having an input lead and an output lead, saidoutput lead connected with the base of said output transistor,
 3. Acircuit as defined in claim 2 wherein said semiconductor coincidencemeans includes a third transistor having multiple emitters and acollector, said multiple emitters coupled to said input terminal, saidcollector coupled to said base of said first transistor, said thirdtransistor in response to signals applied to said input terminalsenabling said first transistor to conduction.
 4. A circuit as defined inclaim 3 wherein said semiconductor feedback means includes a fourthtransistor having a base and an emitter, said base coupled to saidsupply terminal, said emitter coupled to said impedance means and to thecollector of said first transistor, said fourth transistor whenconductive applying a selective overdrive signal to said collector ofsaid first transistor for accelerating the switching operation of saidoutput transistor.
 4. semiconductor coincidence means formed in saidsingle block of semiconductor material and having input leads coupled tosaid input terminals and an output lead coupled to said input lead ofsaid transforming means, said semiconductor coincidence means inresponse to signals applied to said input terminals enabling saidtransforming means and controlling the emitter-controller conduction ofsaid output transistor,
 5. semiconductor feedback means formed in saidsingle block of semiconductor material and receiving a feedback signalcorresponding to the signal at at least one terminal selected from saidoutput terminal and said supply terminal, said semiconductor feedbackmeans responsive to said feedback signal for applying a selectiveoverdrive signal to said transforming means for accelerating theswitching operation of said output transistor, and
 6. impedance meansincluding a resistor and diode having its anode connection distributedalong said resistor, said impedance means coupled to said semiconductorfeedback means and said output transistor for damping inductive kickduring switching of said output transistor.